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Initial Study of a Phase-Aware Scheduling for Hardware Transactional Memory
https://nitech.repo.nii.ac.jp/records/6431
https://nitech.repo.nii.ac.jp/records/6431be25b216-2d50-4a94-8d70-18fcb9e5639e
名前 / ファイル | ライセンス | アクション |
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本文_fulltext (767.8 kB)
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(C)2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2019-03-29 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Initial Study of a Phase-Aware Scheduling for Hardware Transactional Memory | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Tajimi, Tomoki
× Tajimi, Tomoki× Hirota, Anju× Shioya, Ryota× Goshima, Masahiro× Tsumura, Tomoaki |
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著者別名 | ||||||
姓名 | 津邑, 公暁 | |||||
書誌情報 |
en : 2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) p. 1-6, 発行日 2017 |
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出版者 | ||||||
出版者 | IEEE | |||||
ISBN | ||||||
識別子タイプ | ISBN | |||||
関連識別子 | 9781538607015 | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | http://doi.org/10.1109/PACRIM.2017.8121912 | |||||
関連名称 | 10.1109/PACRIM.2017.8121912 | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | Victoria, B.C., Canada, 21-23 August 2017 | |||||
フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf |