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Hardware Implementation of the High-Dimensional Discrete Torus Knot Code
https://nitech.repo.nii.ac.jp/records/4937
https://nitech.repo.nii.ac.jp/records/4937cf4bbe21-9405-4e53-8989-bf55d6cd4569
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
本文_fulltext (1.5 MB)
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Copyright(c)2001 IEICE http://search.ieice.org/index.html
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||||||||||
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| 公開日 | 2013-06-25 | |||||||||||||||||
| タイトル | ||||||||||||||||||
| タイトル | Hardware Implementation of the High-Dimensional Discrete Torus Knot Code | |||||||||||||||||
| 言語 | en | |||||||||||||||||
| 言語 | ||||||||||||||||||
| 言語 | eng | |||||||||||||||||
| 資源タイプ | ||||||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||||||
| 資源タイプ | journal article | |||||||||||||||||
| 著者 |
Hamasuna, Yuichi
× Hamasuna, Yuichi
× Yamamura, Masanori
× Ishizaka, Toshio
× Matsuo, Masaaki
× Hata, Masayasu
× Takumi, Ichi
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| 著者別名 | ||||||||||||||||||
| 姓名 | 内匠, 逸 | |||||||||||||||||
| bibliographic_information |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E84-A, 号 4, p. 949-956, 発行日 2001-04-01 |
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| 出版者 | ||||||||||||||||||
| 出版者 | Institute of Electronics, Information and Communication Engineers | |||||||||||||||||
| 言語 | en | |||||||||||||||||
| ISSN | ||||||||||||||||||
| 収録物識別子タイプ | ISSN | |||||||||||||||||
| 収録物識別子 | 0916-8508 | |||||||||||||||||
| item_10001_source_id_32 | ||||||||||||||||||
| 収録物識別子タイプ | NCID | |||||||||||||||||
| 収録物識別子 | AA10826239 | |||||||||||||||||
| 出版タイプ | ||||||||||||||||||
| 出版タイプ | VoR | |||||||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||||||||
| 内容記述 | ||||||||||||||||||
| 内容記述タイプ | Other | |||||||||||||||||
| 内容記述 | The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations. | |||||||||||||||||
| 言語 | en | |||||||||||||||||
