@inproceedings{oai:nitech.repo.nii.ac.jp:00003466,
 author = {Ikegaya, Tomoki and Oda, Ryosuke and Yamada, Tatsuhiro and Tsumura, Tomoaki and Matsuo, Hiroshi and Nakashima, Yasuhiko},
 book = {Proc. of Int'l. Symp. on System-on-Chip 2011 (SoC2011)},
 month = {Oct},
 note = {application/pdf, We have proposed an auto-memoization processor based on computation reuse, and merged it with speculative multi-threading based on value prediction into a parallel speculative execution. In the parallel speculative execution model, speculative cores do not work when the target instruction region is not suitable for computation reuse. This paper proposes a new parallel speculative execution model where the idle speculative cores execute scout threads for reducing cache miss penalties. The scout thread is based on value prediction, and can handle an instruction region which accesses the addresses with several strides. It also can reduce execution cycles by raising computation reuse ratio. The result of the experiment with SPEC CPU95 FP suite benchmarks shows that the new hybrid model of parallel speculative execution and scout threading improves the maximum speedup from 40.6% to 41.3%, and the average speedup from 15.0% to 19.1%.},
 pages = {22--28},
 publisher = {Institute of Electrical and Electronics Engineers},
 title = {A hybrid model of speculative execution and scout threading for auto-memoization processor},
 year = {2011}
}