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A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations
https://nitech.repo.nii.ac.jp/records/3458
https://nitech.repo.nii.ac.jp/records/3458d8bcd03a-1852-464d-b54e-ce2bf37ca045
| 名前 / ファイル | ライセンス | アクション |
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本文_fulltext (3.7 MB)
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(c)2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
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| Item type | 会議発表論文 / Conference Paper(1) | |||||||||||||
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| 公開日 | 2012-11-07 | |||||||||||||
| タイトル | ||||||||||||||
| タイトル | A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations | |||||||||||||
| 言語 | en | |||||||||||||
| 言語 | ||||||||||||||
| 言語 | eng | |||||||||||||
| 資源タイプ | ||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||||||
| 資源タイプ | conference paper | |||||||||||||
| 著者 |
Ikegaya, Tomoki
× Ikegaya, Tomoki
× Tsumura, Tomoaki
× Matsuo, Hiroshi
× Nakashima, Yasuhiko
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| 著者別名 | ||||||||||||||
| 識別子Scheme | WEKO | |||||||||||||
| 識別子 | 8669 | |||||||||||||
| 識別子Scheme | NRID | |||||||||||||
| 識別子URI | http://rns.nii.ac.jp/nr/1000000335233 | |||||||||||||
| 識別子 | 1000000335233 | |||||||||||||
| 姓名 | 津邑, 公暁 | |||||||||||||
| 著者別名 | ||||||||||||||
| 識別子Scheme | WEKO | |||||||||||||
| 識別子 | 8515 | |||||||||||||
| 識別子Scheme | NRID | |||||||||||||
| 識別子URI | http://rns.nii.ac.jp/nr/1000000219396 | |||||||||||||
| 識別子 | 1000000219396 | |||||||||||||
| 姓名 | 松尾, 啓志 | |||||||||||||
| 書誌情報 |
en : Proc. of Int'l Conf. on Networking and Computing (ICNC'10) p. 63-70, 発行日 2010-11-17 |
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| 出版者 | ||||||||||||||
| 出版者 | Institute of Electrical and Electronics Engineers | |||||||||||||
| 言語 | en | |||||||||||||
| 著者版フラグ | ||||||||||||||
| 出版タイプ | AM | |||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||||
| DOI | ||||||||||||||
| 関連タイプ | isVersionOf | |||||||||||||
| 識別子タイプ | DOI | |||||||||||||
| 関連識別子 | http://dx.doi.org/10.1109/IC-NC.2010.46 | |||||||||||||
| 関連名称 | 10.1109/IC-NC.2010.46 | |||||||||||||
| 内容記述 | ||||||||||||||
| 内容記述タイプ | Other | |||||||||||||
| 内容記述 | We have proposed an auto-memoization processor based on computation reuse, and merged it with speculative multithreading based on value prediction into a parallel early computation. In the past model, the parallel early computation detects each iteration of loops as a reusable block. This paper proposes a new parallel early computation model, which integrates multiple continuous iterations into a reusable block automatically and dynamically without modifing executable binaries. We also propose a model for automatically detecting how many iterations should be integrated into one reusable block. Our model reduces the overhead of computation reuse, and further exploits reuse tables. The result of the experiment with SPEC CPU95 FP suite benchmarks shows that the new model improves the maximum speedup from 40.5% to 57.6%, and the average speedup from 15.0% to 26.0%. | |||||||||||||
| 言語 | en | |||||||||||||
