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Interface properties of SiO2/n-GaN metal-insulator-semiconductor structures
https://nitech.repo.nii.ac.jp/records/5068
https://nitech.repo.nii.ac.jp/records/50683dcb1924-5e2a-40aa-a9ab-030dc7c88e29
| 名前 / ファイル | ライセンス | アクション |
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本文_fulltext (67.2 kB)
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Copyright (2002) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics.The following article appeared in Applied physics letters, 80(25),pp.4756 -4758; 2002 and may be found at http://link.aip.org/link/?apl/80/4756
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 公開日 | 2012-11-06 | |||||||||
| タイトル | ||||||||||
| タイトル | Interface properties of SiO2/n-GaN metal-insulator-semiconductor structures | |||||||||
| 言語 | en | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| 著者 |
Nakano, Yoshitaka
× Nakano, Yoshitaka
× Jimbo, Takashi
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| 著者別名 | ||||||||||
| 姓名 | 神保, 孝志 | |||||||||
| bibliographic_information |
en : APPLIED PHYSICS LETTERS 巻 80, 号 25, p. 4756-4758, 発行日 2002-06-24 |
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| 出版者 | ||||||||||
| 出版者 | American Institute of Physics | |||||||||
| 言語 | en | |||||||||
| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0003-6951 | |||||||||
| item_10001_source_id_32 | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AA00543432 | |||||||||
| 出版タイプ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| item_10001_relation_34 | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | http://dx.doi.org/10.1063/1.1486266 | |||||||||
| 関連名称 | 10.1063/1.1486266 | |||||||||
| 内容記述 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | Electrical characterization of SiO2/n-GaN metal-insulator-semiconductor structures fabricated on sapphire substrates was performed by using high-frequency pulsed capacitance-voltage and capacitance-transient techniques. Fast and slow capacitance transients are clearly seen after applying reverse voltages, reflecting thermal emissions of carriers from the SiO2/GaN interface. The temperature dependence of the capacitance-voltage characteristics shows capacitance saturation in deep depletion (>15 V), which is probably associated with the slow capacitance transient. Deep-level transient spectroscopic measurements reveal two interface traps with activation energies of 0.71 and ?0.76 eV from the conduction band, corresponding to the fast and slow capacitance transients, respectively. Therefore, the observed capacitance saturation may be due to Fermi-level pinning induced by the latter interface trap. | |||||||||
| 言語 | en | |||||||||
