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A hybrid model of speculative execution and scout threading for auto-memoization processor
https://nitech.repo.nii.ac.jp/records/3466
https://nitech.repo.nii.ac.jp/records/3466ab7b437e-9fa6-49a7-89f7-1461a5f177de
| 名前 / ファイル | ライセンス | アクション |
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本文_fulltext (3.2 MB)
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(c)2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
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| Item type | 会議発表論文 / Conference Paper(1) | |||||||||||||||||
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| 公開日 | 2012-11-07 | |||||||||||||||||
| タイトル | ||||||||||||||||||
| タイトル | A hybrid model of speculative execution and scout threading for auto-memoization processor | |||||||||||||||||
| 言語 | en | |||||||||||||||||
| 言語 | ||||||||||||||||||
| 言語 | eng | |||||||||||||||||
| 資源タイプ | ||||||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||||||||||
| 資源タイプ | conference paper | |||||||||||||||||
| 著者 |
Ikegaya, Tomoki
× Ikegaya, Tomoki
× Oda, Ryosuke
× Yamada, Tatsuhiro
× Tsumura, Tomoaki
× Matsuo, Hiroshi
× Nakashima, Yasuhiko
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| 著者別名 | ||||||||||||||||||
| 識別子Scheme | WEKO | |||||||||||||||||
| 識別子 | 8669 | |||||||||||||||||
| 識別子Scheme | NRID | |||||||||||||||||
| 識別子URI | http://rns.nii.ac.jp/nr/1000000335233 | |||||||||||||||||
| 識別子 | 1000000335233 | |||||||||||||||||
| 姓名 | 津邑, 公暁 | |||||||||||||||||
| 著者別名 | ||||||||||||||||||
| 識別子Scheme | WEKO | |||||||||||||||||
| 識別子 | 8515 | |||||||||||||||||
| 識別子Scheme | NRID | |||||||||||||||||
| 識別子URI | http://rns.nii.ac.jp/nr/1000000219396 | |||||||||||||||||
| 識別子 | 1000000219396 | |||||||||||||||||
| 姓名 | 松尾, 啓志 | |||||||||||||||||
| 書誌情報 |
en : Proc. of Int'l. Symp. on System-on-Chip 2011 (SoC2011) p. 22-28, 発行日 2011-10-31 |
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| 出版者 | ||||||||||||||||||
| 出版者 | Institute of Electrical and Electronics Engineers | |||||||||||||||||
| 言語 | en | |||||||||||||||||
| 著者版フラグ | ||||||||||||||||||
| 出版タイプ | AM | |||||||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||||||||
| DOI | ||||||||||||||||||
| 関連タイプ | isVersionOf | |||||||||||||||||
| 識別子タイプ | DOI | |||||||||||||||||
| 関連識別子 | http://dx.doi.org/10.1109/ISSOC.2011.6089225 | |||||||||||||||||
| 関連名称 | 10.1109/ISSOC.2011.6089225 | |||||||||||||||||
| 内容記述 | ||||||||||||||||||
| 内容記述タイプ | Other | |||||||||||||||||
| 内容記述 | We have proposed an auto-memoization processor based on computation reuse, and merged it with speculative multi-threading based on value prediction into a parallel speculative execution. In the parallel speculative execution model, speculative cores do not work when the target instruction region is not suitable for computation reuse. This paper proposes a new parallel speculative execution model where the idle speculative cores execute scout threads for reducing cache miss penalties. The scout thread is based on value prediction, and can handle an instruction region which accesses the addresses with several strides. It also can reduce execution cycles by raising computation reuse ratio. The result of the experiment with SPEC CPU95 FP suite benchmarks shows that the new hybrid model of parallel speculative execution and scout threading improves the maximum speedup from 40.6% to 41.3%, and the average speedup from 15.0% to 19.1%. | |||||||||||||||||
| 言語 | en | |||||||||||||||||
